Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor includes two conductive plates. The top plate of each capacitor is typically shared, or common, with each of the other capacitors. This plate is referred to as the “cell plate.” The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each such memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line decoder and to a digit line decoder. The word line decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The digit line decoder selects a digit line pair in response to the digit line address. For a read operation the selected word line activates the access transistors for a given word line address, and data is latched to the digit line pairs.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell area and its accompanying capacitor area, since capacitance is a function of plate area. Additionally, there is a continuing goal to further decrease memory cell area.
A principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom plate of the capacitor.
Another method of increasing cell capacitance is through the use of high surface area materials such as hemispherical grain polysilicon (HSG) which increase available surface area for a given foot print due to their roughened or irregular surfaces.
As cell area decreases, container structures must be formed in closer proximity to neighboring container structures. At close proximity, a danger exists that conductive fragments will rest on the tops of the container structures, bridging between neighboring container structures and thus acting as a short circuit. Such conductive fragments may be pieces of a container dislodged or broken off during cell formation. Fragments from HSG container structures are often referred to as “grapes” or “floaters.” Capacitors produced from such shorted container structures will result in defective memory cells, as the cells will be unable to accurately store data.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved container structure and methods of producing same.